This invention relates to plasma etch prcesses and, in particular, to a process for forming deep trenches in monocrystalline silicon.
It is well known in the art to isolate devices by way of a trench surrounding the devices. It is also known that this trench can be formed using plasma etching techniques. While shallow grooves are suitable for bipolar or dynamic memory applications, deeper grooves are necessary for MOS applications. It is desired that these grooves not only be deeper, but have vertical or nearly vertical sidewalls and be relatively uniform in depth. For shallow grooves, e.g. two to three microns deep, these criteria are more easily met than for deep grooves, e.g. five or more microns in depth. Further, it is desired that the etch time not double or triple for a groove two or three times as deep.
It is important that the grooves have vertical or nearly vertical sidewalls since devices have already been formed on the wafer. The spacing of the devices is often critical. Thus, the groove or well should not change size, shape, or position with depth. This discussed in some contexts as "loss of critical dimension." In other contexts, it may be referred to as "constant image transfer" during a process.
A considerable variety of gases have been proposed for use in plasma reactors. Various noble or other elemental gase, methanes, ethanes, and gaseous compounds, typically halides, have been used. The particular gas or gas mixture chosen is determined empirically, depending in part on the composition of the wafer to be treated. Even so, the results produced often vary with the equipment being used. For example, the results obtained from a barrel reactor may not be the same as those produced in a parallel plate reactor.
It is known in the art to use a mixture of Freon 11 (CFCl.sub.3) and helium in a plasma etch reactor, e.g. see U.S. Pat. No. 4,353,777. It is also known to use a mixture of sulphur hexafluoride and helium in a plasma reactor, e.g. see U.S. Pat. No. 4,380,489. Both of these patents describe wide gap, parallel plate reactors. Further, the etch rate, for polysilicon, is a maximum of 0.74 microns per minute in patent '777 and 0.13 microns per minute in patent '489.
In view of the foregoing, it is therefore an object of the present invention to provide an improved process for etching silicon.
Another object of the present invention is to provide a process for rapidly etching trenches in silicon.
A further object of the present invention is to provide an improved etch process for narrow gap, parallel plate reactors.